A SDRAM outputs a parallel data signal and a strobe signal at the same timing. Therefore, a read control circuit for the SDRAM delays the phase of the strobe signal by 90 degrees relative to the parallel data signal output from the SDRAM and captures the parallel data signal at an edge of the delayed strobe signal.
A delay circuit is used for delaying a strobe signal. At a low speed (transfer rate) of reading a parallel data signal from a SDRAM, a stable read operation can be performed even if the delay amount of the delay circuit is fixed at a specific amount.
However, as the transfer rate becomes higher, the timing deviation among data bits of the parallel data signal or between the parallel data signal and the strobe signal cannot be ignored. The timing deviation is caused by the effect of change in supply voltage and temperature (VT change) at a higher transfer rate. Therefore, when the delay amount of the delay circuit is fixed at a specific amount, it is difficult to perform a stable read operation at a higher transfer rate.
For the reason above, a technique has been proposed to measure the maximum and minimum delay amounts settable at the delay circuit and to set a delay amount to the median value of the maximum and minimum delay amounts. However, this technique takes time for delay-amount setting. Therefore, the delay-amount setting has been conventionally performed only at the time of power-on or resetting. This leads to voltage or temperature fluctuation during an ordinary read-out operation of the SDRAM. By the fluctuation, even if a timing between data bits and a timing between the data bit and the strobe signal fluctuate, it was impossible to set delay-amount in real time in conformity to the fluctuation.